The advantages of highly flexible memory blocks may be very desirable in structured application specific integrated circuit (ASIC) design, for example. A structured ASIC system often includes embedded memory system, which may be used to provide various types of memory functions. A common configurable random access memory (RAM) block may be arrayed multiple times across a structured ASIC chip, and this solo memory design may be used to serve various functions, such as first-in-first-out (FIFO) buffer, shift register, internet protocol (IP) packet buffer, system cache, video frame buffer, and processor code storage to name a few. Some of these applications require deeper depth but narrower width, while others require wider width but shallower depth. With the broad range of applications of structural ASIC devices, for example, the digital consumer, industrial, wireless, wireline, automotive and military markets, a versatile memory design may be highly desirable.
A versatile memory design may include the ability to be configured to different write policies. A write operation of a memory system can be categorized into three categories based on the reflected data at the output port, namely, no-read-on-write policy, read-before-write policy, and read-after-write policy. No-read-on-write policy refers to the basic write operation, where there is no read operation required when a write command is issued. In a no-read-on-write policy, the only operation executed when a write command is issued is the write operation, and the data output remains unchanged. Read-before-write policy enables the memory to do a read operation first from the memory location specified by ADDRESS[N:0] before overwriting the content of that memory location with the write data. The output will reflect the previously stored data. Read-after-write policy enables the memory to do a read operation on the memory location specified by the ADDRESS[N:0] after overwriting the content of the memory location with the write data. The output will reflect the new data being written into the memory.
In certain applications, for example, data shifting over time in a finite impulse response (FIR) filter equation, the memory may advantageously be able to read the previously stored data before writing new data to the same memory location, which effectively is a read-before-write operation. In other applications, for example, a comparator, it may be advantageous for the memory to write new data before reading the new data from the same memory location, which effectively is a read-after-write operation. In a conventional memory system, a back-to-back read and write would normally need at least two clock cycles.
Methods employed for personalizing memory configurations can be divided into two categories: static configuration and dynamic configuration. Static configuration in this context may be done through via programming, which may be a single layer of vias or multiple layers of vias. Dynamic configuration in this context may be done through the usage of multiplexer.
Some approaches of configuring read or write with a variety of data widths have been described in U.S. Pat. No. 7,157,937 B2. This patent describes a configurable logic array that may include: a multiplicity of logic cells, a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations may all be done on a single via layer.
In view of the above, it would be desirable to have an easily customizable memory structure that may be customized to implement various read-write policies.